cym9291 1m x 36 pipelined nobl? sram module advance information cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 june 7, 2000 features ? operates at 133 mhz uses 512k x 18 high-performance pipelined nobl? synchronous srams 2.5v data inputs/outputs functional description the cym9291 is a high-performance synchronous pipelined nobl memory module organized as 1m by 36 bits. these modules are constructed from 512k x 18 nobl srams in plastic surface mount packages on an epoxy laminate board with pins. the modules are designed to be incorporated into large memory arrays. the module is configured as two banks, where each bank has separate chip select controls. separate clocks are provided for every pair of srams. multiple ground pins and on-board decoupling capacitors en- sure high performance with maximum noise immunity. all components on the modules are surface mounted on a multi-layer epoxy laminate (fr-4) substrate. logic block diagram - cym9291 d[35:0] a[18:0] clk[0:1] a 18:0 oe oe (2) 512k x 18 srams a 18:0 oe clk (2) 512k x 18 srams bw[0] bw[1] bw[0] bw[1] clk[0] clk[1] clk[1] clk[0] ms 0 d[15:0] dp[1:0] d[15:0] dp[1:0] adv/ld adv/ld adv/ld clk cen cen bank 0 bank 1 ms 0 ms 0 oe oe we we we mode mode gnd gnd gnd cs 1 cs2 cs 3 gnd a 19 cs 1 cs2 cs 3 v cc a 19 a 19 d[35:18] d[17:0] d[35:18] d[17:0] sram0 sram1 sram2 sram3 nobl is a trademark of cypress semiconductor corporation.
cym9291 advance information 2 selection guide nobl pipelined module part number cache size sram ? s used system clock (mhz) data t cdv cym9291pz-133 1m x 36 4 of 512k x 18(tqfp) 133 4.4 ns cym9291pz-117 1m x 36 4 of 512k x 18(tqfp) 117 4.8ns
cym9291 advance information 3 pin configuration top view dual read-out zip 10 9 56 78 4 1 2 gnd gnd a 12 3 90 89 85 86 87 88 84 81 82 83 20 19 15 16 17 18 14 11 12 13 30 29 25 26 27 28 24 21 22 d 22 23 39 35 36 37 38 34 31 32 d 20 33 40 41 42 52 51 47 48 49 50 46 43 44 d 26 d 18 a 3 d 16 45 57 58 59 60 56 53 54 v cc2 a 2 55 69 65 66 67 68 64 61 62 gnd 63 70 79 75 76 77 78 74 71 72 73 80 100 99 95 96 97 98 94 91 92 93 d 110 109 105 106 107 108 104 101 102 103 d 32 120 119 115 116 117 118 114 111 112 113 d 19 d 28 a 8 v cc2 gnd a 14 v cc2 d 34 ms [0] gnd a 10 gnd gnd v cc2 a 1 a 0 a 9 a 11 a 5 clk0 clk1 d 1 d 14 a 17 a 16 a 15 adv/ld v cc2 v cc2 we gnd gnd a 13 v cc2 v cc2 oe gnd v cc2 a 19 gnd a 7 a 4 a 18 a 6 gnd v cc2 gnd gnd gnd gnd gnd v cc2 gnd gnd d 0 d 2 d 24 d 3 d 4 d 5 d 11 d 7 v cc2 d 9 d 8 d 10 d 6 d 13 d 12 d 15 v cc2 d 17 d 27 d 31 d 30 v cc2 pd 1 (gnd) gnd gnd gnd gnd gnd gnd gnd d 35 d 33 d 29 23 d 25 gnd gnd gnd gnd gnd gnd gnd gnd gnd pd0(gnd) gnd gnd gnd d 21 gnd (ms [1])nc v cc2 v cc2
cym9291 advance information 4 pin definitions signal description v cc2 2.5v supply gnd ground a[19:0] addresses from processor oe output enable we write enable ms [0] chip select for the module pd 0 ? pd 1 presence detect output pins d[35:0] data lines from processor clk[0:1] clock lines to the module adv/ld advance load signal from processor nc signal not connected on module nc(pin 113) reserved for depth expansion rsvd reserved presence detect pins pd 1 pd 0 cym9291pz - 1m x 36 gnd gnd
cym9291 advance information 5 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 55 c to +125 c ambient temperature with power applied........................................... 0 c to +70 c supply voltage to ground potential .............. ? 0.3v to +3.6v dc voltage applied to outputs in high z state .............................................. ? 0.3v to +3.6v dc input voltage ........................................... ? 0.5v to +3.6v output current into outputs (low) ............................. 20 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.5v 5% electrical characteristics over the operating range parameter description test condition min. max. unit v ih input high voltage 1.7 v cc + 0.3 v v il input low voltage ? 0.3 0.7 v v oh output high voltage v cc = min. i oh = ? 1 ma 2.0 v v ol output low voltage v cc = min. i ol = 1 ma 0.2 v i cc (9291) v cc operating supply current v cc = max., i out =0 ma, f=f max =1/t rc 1680 ma capacitance [1] parameter description test conditions max. unit c a address input capacitance t a = 25 c, f = 1 mhz, v cc = 2.5 v 24 pf c i control input capacitance t a = 25 c, f = 1 mhz, v cc = 2.5 v 24 pf c o input/output capacitance t a = 25 c, f = 1 mhz, v cc = 2.5 v 16 pf c clk clock capacitance t a = 25 c, f = 1 mhz, v cc = 2.5 v 6 pf note: 1. tested initially and after any design or process changes that may affect these parameters. 3.0v gnd output r=351w r=351w 5pf including jig and scope (a) (b) all input pulses output r l =50w z 0 =50w v l = 1.25v 2.5v ac test loads and waveforms
cym9291 advance information 6 switching characteristics over the operating range [2] 133 117 parameter description min. max. min. max. unit clock t cyc clock cycle time 7.5 8.6 ns f max maximum operating frequency 133 117 mhz t ch clock high 2.5 3 ns t cl clock low 2.5 3 ns output times t cdv data output valid after clk rise 4.4 4.8 ns t eov oe low to output valid [3, 5] 4.4 4.8 ns t doh data output hold after clk rise 2.3 2.3 ns t chz clock to high-z [3, 4, 5] 3. 8 3.8 ns t clz clock to low-z [3, 4, 5] 2.3 2.3 ns t eohz oe high to output high-z [3, 4, 5] 3.8 3.8 ns t eolz oe low to output low-z [3, 4, 5] 0 0 ns set-up times t as address set-up before clk rise 1.5 1.5 ns t ds data input set-up before clk rise 1.5 1.5 ns t wes we set-up before clk rise 1.5 1.5 ns t als adv/ld set-up before clk rise 1.5 1.5 ns t ces chip selects set-up 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t weh we hold after clk rise 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 ns t ceh chip selects hold after clk rise 0.5 0.5 ns notes: 2. a/c test conditions assume signal transition time of 2 ns or less, timing reference levels, input pulse levels and output loa ding shown in ac test load for 2.5v devices. 3. t chz , t clz , t oev , t eolz , and t eohz are specified with ac test conditions shown in part (a) of ac test loads. transition is measured 200 mv from steady-state voltage. 4. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 5. this parameter is sampled and not 100% tested.
cym9291 advance information 7 switching waveforms read/write/deselect timing clk address ms [0] we 1a data in/out t cyc t ch t cl ra1 t ah t as t ws t wh t ces t ceh t co q4 q1 = don ? t care = undefined out d2 in d5 in out read write deselect write read read read ignore read deselect deselect wa2 ra3 ra4 wa5 ra6 ra7 t clz t doh 1a q3 out t chz all chip enables need to be active in order to select the device. any chip enable can deselect the device. device originally deselected rax stands for read address x, wax stands for write address x, dx stands for data-in for location x, q7 out t chz t cens t cenh t doh read/write/deselect sequence q6 out t ds t dh qx stands for data-out for location x. adv/ld held low. oe held low.
cym9291 advance information 8 burst timing switching waveforms (continued) adv/ld clk address ms [0] 1a data- in/out t cyc t ch t cl t als t alh ra1 t ah t as t ces t ceh t co q1 = don ? t care = undefined out begin read burst read t clz t doh all chip enables need to be active in order to select the device. any chip enable can deselect the device. rax stands for read address x, wa stands for write address x, dx stands for data-in for location x, qx stands for data-out for device originally deselected location x. cen held low. during burst writes, byte writes can be conducted by asserting the appropriate bw [3:0] wa2 q1+1 out q1+2 out q1+3 out ra3 t clz t chz d2+1 in d2+2 in d2+3 in d2 in t co q3 out t ds t dh burst read burst read begin write burst write burst write burst write begin read burst read burst read burst sequences bw [3:0] t ws t wh we t ws t wh input signals. burst order determined by the state of the mode input. oe held low.
cym9291 advance information 9 switching waveforms (continued) oe three-state i/o ? s oe timing t eohz t eov t eolz ordering information speed (mhz) ordering code package name package type description operating range 133 cym9291pz-133c pzxx 120-pin zip pipelined nobl 1m x 36 commercial 117 CYM9291PZ-117C pzxx 120-pin zip pipelined nobl 1m x 36 document #: 38-01012-**
advance information cym9291 ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams pz13: 120 pin dual sided zip module
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